In the semiconductor arts, it is necessary to perform functional testing on semiconductor devices in order to assure their correct operation. One goal of a functional testing environment is to fully exercise a Device Under Test (DUT.). Some of the most difficult types of transactions associated with a functional test are those having a timing dependency. One example of a timing dependency occurs in systems that have multiple bus masters where both bus masters are attempting to access a single resource at the same time. In order to control signal timing to a DUT, testing schemes have been developed to control which bus master is attempting to access the external resource.
Prior Art FIG. 1 illustrates a system where two bus masters, labeled P1 and P2, can access a DUT at the same time. In the prior art, a bus controller can be used to interact with the masters such that their accesses can be limited. Prior art implementations of the type illustrated in FIG. 1 require the bus controller to interface to the specific bus protocol of the master P1, as well as the master P2. Often, different masters have different protocols, and the bus controller requires additional complexity to account for the differences between various bus masters.
Once a prior art bus controller has been implemented, it monitors the bus waiting for a specific event to occur. An example of one such event would be a write to a specific address. This would be recognized by the bus controller as it monitors the bus master P1. Once the event is recognized by the bus controller, the bus controller asserts control over the master P1 to effectively freezing master P1 from completing the bus cycle of the current or a subsequent instruction. In a similar manner, the bus controller can monitor and control the bus associated with the bus master P2.
Once the bus controller has both processor buses monitored under its control, it would be capable of releasing buses at various times in order to simulate possible system timing situations. Because the prior art bus controller freeze the bus, other bus activity cannot occur while under the control of the bus controller. Therefore, while specific timing may be applied, it is not possible for other system activities to occur.
A need, therefore, exists for a common control mechanism to synchronize the activity of multiple masters that allows the masters to operate in a normal condition during the synching operation.